| 异步时序设计亚稳态的消除方法 |
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| 引用本文： | 丁炜,廖成旺,邓涛,谭耀银.异步时序设计亚稳态的消除方法[J].大地测量与地球动力学,2007,27(Z1):103-105. |
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| 作者姓名： | 丁炜 廖成旺 邓涛 谭耀银 |
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| 作者单位： | 1)中国地震局地震研究所，武汉 4300712)地壳运动与地球观测实验室，武汉 430071 |
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| 摘 要： | 提出一种基于异步比较法产生空满标志位，并利用锁存器实现标志位与时钟同步的FIFO，同时还给出了相应的Verilog HDL代码。该方法能提高时钟频率,节约版图面积。
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| 关 键 词： | 异步先进先出电路 亚稳态 格雷码 Verilog HDL 异步比较法 |
METHODS FOR AVOIDING METASTABILITY OF ASYNCHRONIZATION |
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| Ding Wei,Liao Chengwang,Deng Tao,Tan Yaoyin,.METHODS FOR AVOIDING METASTABILITY OF ASYNCHRONIZATION[J].Journal of Geodesy and Geodynamics,2007,27(Z1):103-105. |
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| Authors: | Ding Wei Liao Chengwang Deng Tao Tan Yaoyin |
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| Institution: | 1)Institute of Seismology,CEA,Wuhan 4300712)Crustal Movement Laboratory, Wuhan 430071 |
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| Abstract: | Based on a novel asynchronous compared method the empty full flags of the FIFO were generated, achieving the flag and clock synchronization by using latches. The related Verilog HDL codes were also illustrated. |
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| Keywords: | asynchronous FIFO(First In First Out) metastablity grad code verilog HDL asynchronous compared |
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