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Statistical Elmore delay of RC interconnect tree
Authors:Dong Gang  Yang Yang  Chai Chang-Chun  Yang Yin-Tang
Affiliation:Microelectronics Institute, Xidian University, Xi'an 710071, China;Microelectronics Institute, Xidian University, Xi'an 710071, China;Microelectronics Institute, Xidian University, Xi'an 710071, China;Microelectronics Institute, Xidian University, Xi'an 710071, China
Abstract:As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.
Keywords:statistical delay  parasitic extraction  RC interconnect  process variations
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