一种可编程逻辑器件在原子钟频率综合电路中的应用

针对被动型铷原子频标电路模块中由三极管等数量众多的分立元件搭建的9倍选频放大模拟电路和种类繁多的集成电路搭建的5.3125 MHz综合器电路,给出了数字化电路解决方案。在此新方案中,通过使用一种复杂可编程逻辑器件对锁相环进行编程控制,可以实现对10 MHz参考信号18倍频的精确控制;同时,利用该复杂可编程逻辑器件内部"虚拟"的集成电路对10MHz参考信号进行分频变换可以得到5.3125MHz信号。实际使用证明,这种设计方案具备易于集成、调试简单的优点,在替换原有模拟倍频、综合器功能电路后,成功实现整机锁定,各项性能指标均达到或优于原有水平,使整机向数字化、小型化迈出重要的一步。

Application of CPLD to frequency synthesizer circuit of atomic clock

A digitalization project is introduced aimming at the circuit-module of passive rubidium atomic frequency standard(RAFS).The circuit-module consisted of a 9-multiple frequency-selective amplification analog circuits and a 5.312 5 MHz synthesizer circuit constituted by a great deal of audions and molectrons.In the new digitalization project,the frequency multiplication from 10 MHz to 180 MHz can be realized accurately by using a complex programmable logic devices(CPLD) to control the phase lock loop(PLL),and a 5.312 5 MHz frequency synthesis is completed by using the inner "virtual" integration circuits of the CPLD.The practice has proved that it is easy to realize integration and easy to debug for this design scheme.After the digital circuit replaced the original circuits in the RAFS,the whole loop-lock can be realized and the performances are better than before,therefore the RAFS unit have made an important step toward digitalization and miniaturization.