| ADSP-TS101S与雷达数字中频接口的FPGA实现 |
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| 引用本文： | 李学华,周伟,刘易,李婧.ADSP-TS101S与雷达数字中频接口的FPGA实现[J].成都信息工程学院学报,2006,21(1):18-21. |
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| 作者姓名： | 李学华 周伟 刘易 李婧 |
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| 作者单位： | 1. 成都信息工程学院电子工程系,四川,成都,610225
2. 成都理工大学自动化工程学院,四川,成都,610059 |
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| 摘 要： | 介绍了ADSP-TS101S与雷达数字中频接口电路原理及其FPGA实现.采用Cyclone芯片设计系统中FIFO缓存、低压差分（LVDS）转换、时钟倍频、控制译码、时序逻辑电路等电路,很好地解决了传统系统中稳定性差,在线升级难等问题,提高了系统的整体性能.
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| 关 键 词： | ADSP-TS101S 雷达数字中频 FIFO Cyclone |
| 文章编号： | 1671-1742(2006)01-0018-04 |
| 修稿时间： | 2005年1月13日 |
Implementation of interface between ADSP-TS101S and radar DIF based on FDGA |
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| LI Xue-hua,ZHOU Wei,LIU Yi,LI Jing.Implementation of interface between ADSP-TS101S and radar DIF based on FDGA[J].Journal of Chengdu University of Information Technology,2006,21(1):18-21. |
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| Authors: | LI Xue-hua ZHOU Wei LIU Yi LI Jing |
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| Abstract: | The working principle of the interface between the ADSP-TS101S and radar DIF and its implementation in FPGA is introduced.The circuit of the FIFO,LVDS conversion,multiple-frequency and control logic within a cyclone chip is realized and the problem in the traditional system with bad system-stability and difficulty of upgrading I-system is settled.As a result it greatly improves the whole performance. |
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| Keywords: | ADSP-TS101S radar DIF FIFO cyclone |
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