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| HASH算法MD5的高速实现 | |
| 引用本文： | 曾旭,高献伟,路而红,陈运.HASH算法MD5的高速实现[J].成都信息工程学院学报,2009,24(2):129-132. |
| 作者姓名： | 曾旭 高献伟 路而红 陈运 |
| 作者单位： | 1. 成都信息工程学院计算机学院,四川,成都,610225;遵义医学院医学信息工程系,贵州,遵义,563003 2. 北京电子科技学院电子系,北京,100070 3. 成都信息工程学院计算机学院,四川,成都,610225 |
| 摘 要： | 在分析HASH算法MD5的基础上详细介绍了目前主流的4种硬件实现方式,给出了其中迭代方式和基于缩短关键路径的循环展开方式的FPGA实现.基于缩短父键路径的循环展开方式有效的压缩了一半的工作时钟数,并提高了吞吐量,是目前所给出的国内外方案中占用硬件资源较小而工作效率较高的硬件实现方式. |
| 关 键 词： | 展开 迭代 |
High-speed implementation of HASH MDS algorithm |
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| ZENG Xu,GAO Xian-wei,LU Er-hong,CHEN Yun.High-speed implementation of HASH MDS algorithm[J].Journal of Chengdu University of Information Technology,2009,24(2):129-132. | |
| Authors: | ZENG Xu GAO Xian-wei LU Er-hong CHEN Yun |
| Institution: | ZENG Xu1,2,GAO Xian-wei3,LU Er-hong3,CHEN Yun1(1.Dept.of Computers,CUIT,Chengdu 610225,China,2.Dept.of Medical & Information,ZMC,Zunyi 563000,3.Dept.of Electronics,BESTID,Beijing 100070,China) |
| Abstract: | Four ways of the hardware implementation are introduced based on the HASH algorithm MD5 and the iterative way and unroll way of them on FPGA are given.The unroll way is based on the condensation of the number of the clock cycle into half,shortens the critical path and increases the throughput.This way is a high efficient hardware implementation and occupies little resource compared with the other both at home and abroad. |
| Keywords: | MD5 FPGA Verilog |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |