| 基于E1接口的时间同步系统关键模块设计与仿真 |
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| 引用本文： | 闫辉,胡永辉,侯雷.基于E1接口的时间同步系统关键模块设计与仿真[J].时间频率学报,2012,35(4):212-217. |
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| 作者姓名： | 闫辉 胡永辉 侯雷 |
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| 作者单位： | 1. 中国科学院国家授时中心,西安710600 中国科学院精密导航定位定时技术重点实验室,西安710600 中国科学院研究生院,北京100039
2. 中国科学院国家授时中心,西安710600 中国科学院精密导航定位定时技术重点实验室,西安710600 |
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| 基金项目： | 中国科学院“西部之光”人才培养计划重点资助项目 |
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| 摘 要： | 针对E1线路延迟稳定的优点，给出了溯源到GPS系统时间的时间保持模块，提出时间信息组合以适应E1线路不成帧的传输方式，采用HDB3码作为E1线路传输码型，利用FPGA芯片EP2C8T14418进行开发，设计了基于E1接口的时间同步系统关键模块，并对各关键模块进行仿真，结果表明各模块设计均满足时间同步系统的要求。
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| 关 键 词： | 时间同步 E1接口 HDB3码 现场可编程门阵列 |
Design and simulation of key modules of time synchronous system based on E1 interface |
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| YAN Hui,HU Yong-hui,HOU Lei.Design and simulation of key modules of time synchronous system based on E1 interface[J].Journal of Time and Frequency,2012,35(4):212-217. |
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| Authors: | YAN Hui HU Yong-hui HOU Lei |
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| Institution: | 1. National Time Service Center, Chinese Academy of Sciences, Xi＇an 710600, China; 2. Key Laboratory for Precision Navigation and Timing Technology, National Time Service Center, Chinese Academy of Sciences, Xi＇an 710600, China; 3. Graduate University of Chinese Academy of Sciences, Beijing 100039, China) |
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| Abstract: | According to the advantage of the stable transfer delay of E 1 interface, the time keeping module which can trace to the time of GPS System is proposed. The time information combination is given in order to adapt to the no framed transfer method for E1 interface. By using the HDB3 code as the transmission code and adopting the EP2C8T14418 FPGA chip, the key time synchronous system module of E1 interface is designed. The simulations of the key modules are conducted and the results indicate that all the key modules meet the requirements of the time synchronization system. |
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| Keywords: | time synchronization E1 interface HDB3 code FPGA |
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