| 一种基于DSP和FPGA的低频时码接收机设计 |
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| 引用本文： | 李国栋,许林生.一种基于DSP和FPGA的低频时码接收机设计[J].时间频率学报,2006,29(1):27-34. |
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| 作者姓名： | 李国栋 许林生 |
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| 作者单位： | 1. 中国科学院国家授时中心,陕西,临潼,710600;中国科学院研究生院,北京,100039
2. 中国科学院国家授时中心,陕西,临潼,710600 |
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| 摘 要： | 介绍了一种基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的低频时码接收机的硬件组成,描述了该接收机系统实现时间同步的方法,阐述了DSP和FP-GA的软件设计,给出了测试和仿真结果。该设计方案具有精度高、可靠性强、扩展性好等优点。
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| 关 键 词： | 低频时码 数字接收机 数字信号处理器 现场可编程门阵列 |
| 文章编号： | 1001-1544（2006）01-0027-08 |
| 收稿时间： | 2006-03-17 |
| 修稿时间： | 2006-05-30 |
A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA |
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| LI Guo-Dong,XU Lin-Sheng.A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA[J].Journal of Time and Frequency,2006,29(1):27-34. |
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| Authors: | LI Guo-Dong XU Lin-Sheng |
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| Institution: | 1 National Time Server Center.Chinese Academy of Sciences,Lintong, Shaanxi 710600,China;2 Graduate University of Chinese Academy of Sciences, Beijing 100039, China |
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| Abstract: | The hardware of a low frequency time-code receiver which was designed with FPGA(field programmable gate array)and DSP(digital signal processor)is introduced.The method of realizing the time synchronization for the receiver system is described.The software developed for DSP and FPGA is expounded,and the results of test and simulation are presented.The design is characterized by high accuracy,good reliability,fair extensibility,etc. |
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| Keywords: | LF time-code signal digital receiver DSP FPGA |
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